library IEEE;
use IEEE.std_logic_1164.all;

entity ffd is
    port (
        d_i     : in  std_logic;
        set_i   : in  std_logic;
        reset_i : in  std_logic;
        nclk_i  : in  std_logic;
        q_o     : out std_logic
    ); 
end ffd;

architecture behav of ffd is

begin

    process(nclk_i, set_i, reset_i)
    begin
        if (set_i = '1') then
            q_o <= '1';
        elsif (reset_i = '1') then
            q_o <= '0';
        elsif (nclk_i = '0' and nclk_i'event) then
            q_o <= d_i;
        end if;
    end process;    

end behav;

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